EE380 Simple Processor Architecture Simulator

This is a cycle-by-cycle simulator for the simple architectural implementation described at http://aggregate.org/EE380/refss.html.

Enter/edit your control and initialization here:
/* This is a demo of how the simulator works.... Comments are done as they are in C, i.e., like this. */ /* Now a simple delay specification... */ delay 5 IN OUT SEL delay 20 ALU delay 15 ALUand ALUor ALUxor /* a little faster */ delay 36 MEM /* just a tad over one clock */ /* In order for JUMPonop to work, you need to define how opcodes are decoded; that's what "when" does. For each different type of instruction, you define a mask and match value; if ((ir & mask) == match), then the next state after JUMPonop will be the labeled one. Note the functions available for formatting fields.... */ when (op()+shamt()+funct()) funct(32) Add when 0xfc000000 0x20000000 Addi /* Just like the EE380 reference description... */ Start: PCout, MARin, MEMread, Yin CONST(4), ALUadd, Zin, UNTILmfc MDRout, IRin Zout, PCin, JUMPonop HALT /* Should end here on undecoded op */ Add: SELrs, REGout, Yin SELrt, REGout, ALUadd, Zin Zout, SELrd, REGin, JUMP(Start) Addi: SELrs, REGout, Yin IRimmedout, ALUadd, Zin Zout, SELrt, REGin, JUMP(Start) /* Initial values... all others are 0 */ $9=0x10000000 /* MEM[0]= MIPS "addi $10,$9,0x50" instruction */ MEM[0]=0x20000000+rs(9)+rt(10)+immed(0x50) /* MEM[4]= MIPS "add $11,$10,$9" instruction */ MEM[4]=funct(32)+rs(9)+rt(10)+rd(11) /* MEM[8]= the easy way to specify the MIPS add */ MEM[8]={add $11,$9,$10} /* MEM[12]= invalid op, causing HALT after JUMPonop */ MEM[12]=0 /* A few final value tests... */ PC#12 10 /* only if sim enough cycles */ $10#0x10000050 5 MEM#2 /* 2 points off per memory error */ MEM[0]#0x20000000+rs(9)+rt(10)+immed(0x50) MEM[4]#{add $0,$9,$10}+rd(11) MEM[8]#0x012a5820 MEM[12]#23 /* like this one */

Maximum number of clock cycles to simulate:

Memory latency: 3 cycle delay 4 cycle delay 5 cycle delay 6 cycle delay 7 cycle delay 8 cycle delay 9 cycle delay 10 cycle delay 11 cycle delay 12 cycle delay 13 cycle delay 14 cycle delay 15 cycle delay 16 cycle delay random delay 1 cycle delay 2 cycle delay

Report conditions at each clock cycle Report only warnings and errors Report timing and final conditions

The final status was a 61% match for that specified.

The following values were wrong: PC MEM[0xc]